Integrated circuit memory devices used for storing data can be divided into volatile memory devices or non-volatile memory devices. When the electric power supplied to the volatile memory devices is interrupted, the volatile memory devices lose data stored in the devices. However, even though the electric power supplied to non-volatile memory devices is interrupted, the non-volatile memory devices keep data stored in the devices. Thus, the non-volatile memory devices, for example, flash memory devices, may be used for memory cards, mobile communication terminals and many other applications.
FIG. 1 is a plan view illustrating a portion of a cell array region of a conventional NAND-type flash memory device.
With reference to FIG. 1, an isolation layer to define a plurality of line shaped active regions 1 is formed at a predetermined region of the cell array region. A string selection line SSL′ and a ground selection line GSL′ are formed to cross over the active regions 1. The string selection line SSL′ and the ground selection line GSL′ are disposed in parallel with each other and closely spaced-apart from each other. A plurality of control gate electrodes WL1′, . . . , WLn′, that is, n word lines WL1′, . . . , WLn′, are provided to cross over the active regions 1 between the string selection line SSL′ and the ground selection line GSL′. A plurality of floating gates 5 are interposed between the control gate electrodes WL1′, . . . , WLn′ and the active regions 1. An insulating interlayer is provided on the substrate including the control gate electrodes WL1′, . . . , WLn′. Bit line contact holes 15 penetrating the insulating interlayer, and bit line contact plugs filling the bit line contact holes 15, are provided. Bit lines 20 covering the bit line contact plugs and overlapping the active regions 1 are provided.
When the integration density of the conventional NAND-type flash memory device of FIG. 1 increases, the pitch of the bit lines 20 and the active regions 1 generally decreases. Nevertheless, the bit lines 20 should have low electrical resistance to allow high speed operation of the NAND-type flash memory device.
To solve the problems due to the decrease in the pitch of the bit lines 20, NAND-type flash memory devices have been suggested, wherein four adjacent strings share one bit line. A NAND-type flash memory device having a shared bit line is disclosed in U.S. Pat. No. 6,151,249 to Shirota et al. As described in this patent, first and second active regions adjacent to each other are formed in a semiconductor substrate, and predetermined regions of the first and second active regions are contacted with one bit line contact plug. Unfortunately, it may be difficult to provide low contact resistance between the bit line contact plug and the active regions.